Improve performance of johnson counter by reduce number of transistors of d flip flop

Abstract

The working of a system is determined by the impact of designing techniques that are implemented over several regions of system. In order to give a smart design & intelligence to design to the computer, a particularized design is requires that can work on low amount of power & has got less complexity. As the computer is comprised of sequential circuitries, there is a need for detecting sequential circuitries in an effective manner & making sure the minimal dissipation of power without any kind of errors & simple architecture. Various counters are taken into account for being cardinal portions of sequential circuitries. In the previous document, a designing schema is considered for developing the Johnson counter along with the required gating of clock that is constituted over toggling operations of J-K FFs. The designing schema is very easy & important than the design based over traditional shift registers as the provided schema furnish lessen interlinks & less dissipation of power. In this paper, we work to enhance the outcome by reduction the amount of transistors of D flip flops. Here, we apply the suggested D-FF in Johnson counter. After the implementation of D-FFs, aggregated amount of transistors will lead to deduction of Johnson counter & area as well. Keywords: clock gating; Johnson Counter; low power VLSI design; power dissipation; sequential circuit