Design and Optimization of 64-Bit Carry Select Adder using TG Technology

Abstract

Many computers and other kinds of processors the adder is the most commonly used arithmetic block. Adder is used in the arithmetic logic units, and also in other parts of the processor, where it is used to calculate addresses, table indices, and similar operations. In this paper, we proposed an area-efficient and high speed carry select adder that also having moderate power consumptions. In this paper, we implemented the carry select adder (CSA) without using multiplexer (MUX) for final selection. The MUX stage replaced by the use of combinational gates. The proposed architecture then compared with the carry select adder having two mux and the carry select adder having one mux. The 64-bit CSA, implemented using TG technology at 1.8 V voltage supply, provides 82% better Power-Delay-Product results when compared with CSA having MUX at 180nm technology. Keywords: carry select adder, area efficient, high speed