A Digital CMOS Implementation with Power Dissipation

Authors

  • Chanchal Rana Dr. Jai Gopal Pandey Department of Electronics and Communication, Jayoti Vidyapeeth Women’s University, Jaipur Rajasthan IC Design Group CSIR-CEERI, Pilani, Rajasthan

Abstract

The power dissipation source of CMOS circuits is presented. Specifically, the main principles of Inversion Duality dynamic, static, Charging and Discharging of Load Capacitances and leakage power dissipation Short-circuit Power Dissipation are illustrated together with the low power strategies for reducing each power component.
Keyword: Digital, CMOS, PMOS, NMOS Static, Dynamic, Power, Function.

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Published

2015-08-30

How to Cite

Dr. Jai Gopal Pandey, C. R. (2015). A Digital CMOS Implementation with Power Dissipation. International Journal of Engineering Technology and Computer Research, 3(4). Retrieved from https://www.ijetcr.org/index.php/ijetcr/article/view/221

Issue

Vol. 3 No. 4 (2015)

Section

Articles

License

Creative Commons LicenseInternational Journal of Engineering Technology and Computer Research (IJETCR) by Articles is licensed under a Creative Commons Attribution 4.0 International License.