VISHAL G. PURANIK2, K. P. S. Design of Low Power Truncation-Error-Tolerant (TET) Adder in Digital Signal Processing. International Journal of Engineering Technology and Computer Research, [S. l.], v. 2, n. 6, 2014. Disponível em: https://www.ijetcr.org/index.php/ijetcr/article/view/76. Acesso em: 6 oct. 2026.