A Review on Analysis of 4-bit Comparator using Different Full-Adder Logic Style with Different Technologies

Abstract

In era of electronics comparator is most important digital combinatorial circuit which compares two digital or analog signals, but outputs alway digital. With enhancement of technology optimization of digital circuit design improving day by day at the cost of complexity .In this review paper some thoughts on performance of different dynamic comparators is discussed. Many versions of dynamic comparator using different logic style of full-adders is proposed. The purpose is to find the high speed, low power and minimum area of dynamic comparator design. There are more than one technique to design CMOS comparators. By using different logic styles of comparators it is used accordance with application in specific need. The comparative analysis of 4-bit comparator architecture using different technologies. The simulation would be done on TANNER EDA using different VLSI technologies CMOS, CPL, DPL, DVL, GDI, TG, CNTFET, GDI and TG. The GDI and TG technologies allow to use less transistor count and power consumption and delay as compare to CMOS logic and lowers the term transistor count as compared to CMOS,CPL and DPL. Keywords: 4-bit Comparator design, CMOS (Complementary Metal Oxide Semiconductor), GDI (Gate Diffusion Input), TG (Transmission Gate), Low Power Dissipation, Delay.